`include "defines.v"
module ysyx_210448_if_stage(
  input wire clk,
  input wire rst,
  input wire stop,
  input wire if_ready,
  input wire r_hs,
  input wire [63:0] if_data_read,
  input wire [63:0]pc_add,
  input reg pc_write,
  output reg [63 : 0] if_pc,
  output reg [31 : 0] if_inst,
  output reg if_id_en,
	output wire if_valid,
  output reg [63:0] if_addr,
  output wire [1:0] if_size,
  output reg if_fetched,
  output wire [3:0] if_read_id,
  output wire if_mem_read,
  output wire if_w_ena,
  output wire if_ar_hand,
  output wire axi_mem_read,
  output wire axi_mem_write
);
assign if_id_en=1'b1;
reg [63:0] addr;
assign if_ar_hand=(if_valid)&&(if_ready);
wire [63:0] if_inst_data;
assign if_read_id=4'b0010;
//对于跳转取到错误的值将其清除
assign if_inst_data=((pc_write==1'b1)&&(if_inst!=32'b0))?64'b0:if_data_read;
always @( posedge clk ) begin
  if (rst) begin
    if_pc <= `PC_START;
    if_addr <=`PC_START;
    if_fetched <= 0;
  end
  else if (if_ar_hand&&~stop) begin
    if_mem_read<=(if_inst_data[6:0]==7'b0000011)?1:0;
    if((pc_write==1'b1)&&(if_inst!=32'h0)) begin
    if_pc<=pc_add;
    if_addr<=pc_add;
    if_fetched<=1; 
    if_inst<=if_inst_data[31:0];
    end
    else begin
    if_pc<=if_addr;
    if_addr<=if_addr + 4;
    if_fetched<= 1;
    if_inst<=if_inst_data[31:0];
    end
  end
  else if(r_hs)
  begin
    if_mem_read<=1'b0;
  end
  else begin
    if_fetched <= 0;
  end
end

assign if_valid =1'b1;
assign axi_mem_read=(if_inst[6:0]==7'b0000011)?1:0;
assign axi_mem_write=(if_inst[6:0]==7'b0100011)?1:0;
assign if_w_ena=((if_inst[6:0]==7'b1100011)||(if_inst[6:0]==7'b0000011)||(if_inst[6:0]==7'b0100011))?0:1;//寄存器使能信号
assign if_size = `SIZE_W;

endmodule
